
DE2-70 User Manual
V_VCC33 VGND
V_VCC33
D83
V_VCC18 AV1_VCC18
PV1_VCC18
C31
0.1u
TD1_D[0..7]
J8
BAT54S
U11
C30
10n
R91
1.74K
VGND
R89
R90
36
39
C26
0.1u
TD1_RESET_n
C27 0.1u
C29 0.1u
C28
0.1u
23
29
30
31
26
25
AIN1
AIN2
AIN3
RESET
VREFN
VREFP
ADV7180
ELPF
P0
P1
P2
P3
P4
P5
P6
P7
19
17
16
10
9
8
7
6
5
RN44
1
2
3
4
5
6
7
8
47
16
15
14
13
12
11
10
9
TD1_D0
TD1_D1
TD1_D2
TD1_D3
TD1_D4
TD1_D5
TD1_D6
TD1_D7
I2C ADDRESS IS 0x40
28MHZ
V_VCC33
13
12
32
18
XTAL
XTAL1
ALSB
PWRDWN
VS/FIELD
HS
SFL
INTRQ
LLC
37
39
2
38
11
R92
R93
120 TD1_VS
120 TD1_HS
TD1_CLK27
I2C_SCLK
I2C_SDAT
34
33
SCLK
SDATA
TEST_0
22
VGND
V_VCC33 VGND
V_VCC33
TD2_D[0..7]
V_VCC18
AV2_VCC18
PV2_VCC18
D84
C37
0.1u
J9
BAT54S
U12
C36
10n
R96
1.74K
RCA JACK
VGND
R94
R95
36
39
C32
0.1u
TD2_RESET_n
C33 0.1u
C34
C35 0.1u 0.1u
23
29
30
31
26
25
AIN1
AIN2
AIN3
RESET
VREFN
VREFP
ADV7180
ELPF
P0
P1
P2
P3
P4
P5
P6
P7
19
17
16
10
9
8
7
6
5
RN45
1
2
3
4
5
6
7
8
47
16
15
14
13
12
11
10
9
TD2_D0
TD2_D1
TD2_D2
TD2_D3
TD2_D4
TD2_D5
TD2_D6
TD2_D7
28MHZ
I2C ADDRESS IS 0x42 V_VCC33
13
12
32
18
XTAL
XTAL1
ALSB
PWRDWN
VS/FIELD
HS
SFL
INTRQ
LLC
37
39
2
38
11
R97
R98
120 TD2_VS
120 TD2_HS
TD2_CLK27
I2C_SCLK 34
I2C_SDAT 33
SCLK
SDATA
TEST_0
22
VGND
Figure 5.18.
TV Decoder schematic.
Signal Name
TD1_D[0]
TD1_D[1]
TD1_D[2]
TD1_D[3]
TD1_D[4]
TD1_D[5]
TD1_D[6]
TD1_D[7]
TD1_HS
TD1_VS
FPGA Pin No.
PIN_A6
PIN_B6
PIN_A5
PIN_B5
PIN_B4
PIN_C4
PIN_A3
PIN_B3
PIN_E13
PIN_E14
53
Description
TV Decoder 1 Data[0]
TV Decoder 1 Data[1]
TV Decoder 1 Data[2]
TV Decoder 1 Data[3]
TV Decoder 1 Data[4]
TV Decoder 1 Data[5]
TV Decoder 1 Data[6]
TV Decoder 1 Data[7]
TV Decoder 1 H_SYNC
TV Decoder 1 V_SYNC